The present disclosure is related to a bus architecture and its method of operation. More particularly, the present disclosure is related to bus architectures and operations that support burst and pipelined transfers.
The Advanced Microcontroller Bus Architecture (AMBA) standard is an open industry bus architecture that may be used for System on Chip (SoC) designs. The bus architecture may incorporate a variety of system components that may include, e.g., a micro-controller, memory interface and blocks of peripheral interface logic. The AMBA architecture may support bandwidths of external memory and an internal bus, on which the microcontroller, on-chip memory and other Direct Memory Access (DMA) type devices may reside. To sustain these bandwidths, the AMBA bus architecture may use different hierarchies of bus interfacing for different transfer applications. High-bandwidth interfacing may be used between components involved with the majority of data transfers; while lower-bandwidth interfacing may be used for the less frequent communication applications.
For example, a high bandwidth bus, e.g., which may be known as an Advanced High-performance Bus (AHB), may be used as a bus interface to a device with on-chip memory and DMA type devices that may support burst and pipelined data transfer procedures. For the pipelined operations, bus grants may be presented before address and control signals, which in turn may be presented before the data. Additionally, the grants, address and control signals of one transfer may overlap the data of a previous transfer(s).
To interface lower bandwidth peripheral devices, a lower bandwidth bus may be used. A bridge may link between the two different buses. For example, a bridging device may interface an AHB-type bus to a peripheral bus. The bridge may allow operations of the higher level bus to proceed while lower bandwidth applications may be concluded or performed on the lower bandwidth bus as might be associated with peripheral interactions, e.g., such as a keyboard, mouse, printer and a programmable input/output. Such peripheral devices may also comprise memory-mapped register interfaces of low-bandwidth protocols, which may allow access under programmable control.
Procedures of the higher performance bus may be referenced as serving a plurality of masters and slaves. For example, a multiplexer may select which of the plurality of masters may drive the address and control signals over the bus. Additionally, one of the masters, as a granted master, may likewise send data across the bus. Or, in an opposite direction (e.g., of a read procedure versus a write procedure), a multiplexer may determine a “slave” of the plurality of slaves to access the bus for sending its data to be read by a “master”. But for purposes of simplicity, the present disclosure, hereinafter, shall reference sourcing devices as “masters”.
In a transfer application, a master may first request access to the bus independent of other possible masters. An arbiter may receive a request and may grant a master access to the bus for transfer operations. The granted bus master of conventional bus architecture may drive the bus with address and control signals to establish parameters of the transfer. The parameters may include, e.g., destination address, direction and size for the transfer. Additionally, the information may establish a packet type, which may indicate a number of packets to be associated with a burst type transfer.
Accordingly, each transfer application may include a plurality of cycles, e.g., grant, address/control and data. The grant cycle may include granting a designated master to access the bus, the address and control cycle may communicate the parameters of the transfer, and other data cycle(s) may be used for the data. An arbiter establishes when a master is to be granted access to the bus. The arbiter may also establish a given start-time and duration for the coupling of the granted master to the bus to avoid multiple masters from driving the bus simultaneously. Typically, such granted masters will, thus, complete transfer procedures before another master is coupled to the bus.
For such high performance bus architectures, it may be understood that the burst and pipelined queuing procedures may include latencies for setting-up the data transfers. As used herein, “latency” may reference durations that may be associated with set-up, e.g., deriving grants, configuring multiplexers and determining transfer parameters. These latencies may seem excessive when not utilizing full capacity burst-type transfers.
In other words, the operative procedures of the conventional burst and pipelining type high-performance buses may seem inefficient for the handling of, e.g., single burst transfers. If every bus master of the bus were using single burst transfers, bus efficiency would drop. For this conventional high-performance-type bus architecture—i.e., of the burst and pipelining operative procedures—the burst type signal of a granted master may be read from an egress side of an access multiplexer. The burst type signal may be read via the multiplexer and after granting the master and coupling it to the bus. Thus, when handling these transfers of single-burst-type, an arbiter might be limited to only one grant for every other bus cycle.